자유게시판

The present invention relates to a VFO (Variadle Frequency) for generating an accurate data window for separating a clock bit and a data bit from a signal read from a floppy disk.
Oscillator) circuit.

[Prior Art] Before describing an example of a conventional VFO circuit for a floppy disk, a data writing format used for a floppy disk and the operation of the VFO circuit will be briefly described. Most of the floppy disk formats are currently in the IBM format or a similar format. Hereinafter, this will be described as an example.

FIG. 3 shows the data pulse train read from the floppy disk drive (FDD) in the case of single density (FM) recording and double density (MFM) recording of an 8-inch floppy disk. FIG. 3 (a) shows the case of FM recording. In the read data pulse train, a clock pulse exists every 4 μs of a 1-bit cell. A bit cell cycle is formed between the clock pulses, and 1,0 of data is defined depending on whether or not a data pulse exists at a reference position within the cell cycle. The data window waveform as shown in the figure is generated by the VFO circuit in synchronization with the timing of this read data pulse train,
By taking the logical sum of the data pulse train and the data window, the data pulse contained in the read data pulse is separated and the separate data pulse is reproduced,
As a result, reproduced data is obtained.

FIG. 3 (b) shows the case of MFM recording. In MFM recording, a clock pulse exists only when the immediately preceding adjacent bit is 0. Also in this case, the data window waveform synchronized with the timing of the read data pulse train is generated by the VFO circuit, and the data pulse is separated by taking the logical product of the two to generate the separate data pulse, and the data is regenerated. In the case of a 5-inch floppy disk called a mini floppy, the bit cell period is twice as long as in the case of 8 inches.

Now, if the read data pulse train from the FDD is exactly at the reference position in the bit cell as shown in FIG. 3, the data window waveform can be created relatively easily by the one-shot multivibrator circuit or the like. But actually 8
The inch standard floppy disk may deviate by up to ± 350 ns from its ideal reference position, and the mini floppy disk may deviate by ± 700 ns. This is called a peak shift, and is a phenomenon that occurs when adjacent read waveforms interfere with each other when reading data from a magnetic medium.

The VFO circuit thus generates a correct data window waveform from the read data pulse train having peak shift,
This circuit separates only the data pulse.

Examples of conventional VFO circuits are described in detail, for example, in the magazine “Interface” July 1979 issue.

FIG. 4 is a block diagram showing a conventional VFO circuit. Sixth
The figure is based on the block diagram of FIG.
3 shows an example of a VFO circuit in detail. Blocks surrounded by single-dot iron lines correspond to the same numbers in FIG. However, the low-pass filter (LPF) has different characteristics for the SYNC field and the data field, but it has a new number 601 because it shares part of the circuit.
The numbers attached to the respective flip-flops in the figure are the model numbers of ICs that are normally used, and refer to books and the like.

The read data from the FDD is input to the terminal 401, and the SYNC field / data field switching signal is input to the terminal 402. The data input to the terminal 401 is input to the phase comparison circuit 404 via the one-shot multivibrator 403. Voltage controlled oscillator (VCO)
illator) 408 is an oscillating circuit for generating a window waveform, and the output signal from VCO 408 is input to phase comparison circuit 404 via gate circuit 410 and is compared in phase with the output of one-shot multivibrator 403. The output of the phase comparison circuit 404 is passed through the switch circuit 405, the high frequency component is removed by the first or second low pass filter (LPF) 406 or 407, and the result is input to the VCO 408. Based on the phase comparison result, the oscillation frequency of the VCO 408 is determined. (Ie window signal frequency and phase)
Control. That is, the phase comparison circuit 404, LPF
406 or 407, VCO 408 constitutes a phase locked loop (PLL). The PLL does not follow a fast fluctuation due to the peak shift of the read data pulse train input to the terminal 401, but generates a signal whose phase always follows (synchronizes) with a slow fluctuation.

The LPE is the first LPF with fast response (high cutoff frequency).
The second LPF 407 that responds slowly to 406 (low cutoff frequency)
There are two types, which are switched by the switch circuit 405.

Here, the operation outline of FIG. 4 will be described with reference to the time chart of FIG. FIG. 5 is a time chart in the case of the FM recording shown in FIG.

The read data pulse train of FIG. 5A from the FDD is input to the terminal 401. In FIG. 5, the first half is the SYNC field for synchronizing the window waveform with the clock pulse that determines the bit cell period in the read data pulse train, and the second half is the data field that follows the SYNC field. One-shot multivibrator 403 is triggered by the read data pulse train,
The one-shut pulse shown in FIG. 5B is output to the phase comparison circuit 404. On the other hand, the VCO 408 outputs the window waveform shown in FIG. The gate circuit 410 switches the output to the phase comparison circuit 404 between the SYNC field and the data field based on the SYNC field / data field switching signal input to the terminal 402. 5 (c)) is output, and in the case of the data field, the waveform of FIG. 5 (d) is output.
Further, the phase comparison circuit 404 compares the outputs of the one-shot multivibrator 403 and the gate circuit 410, controls the VCO 408 via the LPF 406 in the SYNC field, and controls the VCO 408 via the LPF 407 in the data field. . Further, the waveform shaping circuit 409 generates the output of FIG. 5 (e) based on the output of the gate circuit 410 of FIG. 5 (d). As a result, the data is reproduced by taking the logical product of the window waveform of FIG. 5 (c) and the data pulse of FIG. 5 (d) in the data field.

Next, the operation of the conventional VFO circuit will be specifically described in detail.

a) First, switching of the LPFs 406 and 407 will be described.

In order to synchronize with a floppy disk, a pulse train called a SYNC field at equal intervals is written at the beginning of each sector. In the SYNC field, the pulse trains recorded are evenly spaced, so no peak shift occurs in this portion. In this part, the first LPF406, which has a fast response, is used.
Quickly synchronize with the SYNC bit. Subsequently, after entering the data field where the recording data is read, the switch circuit 405 switches to the LPF 407 having a slow response so that the fluctuation of the pulse train interval due to the peak shift is not responded. A SYNC field / data field switching signal, which is a signal for switching, is given to the terminal 402. This signal can be supplied by the processor or floppy disk controller of a system using FDD.

b) Next, the functions of the one-shot multivibrator 403, the gate circuit 410, the phase comparison circuit 404, and the output waveform shaping circuit 409 will be described with reference to the circuit configuration of FIG. 6 and the time chart of FIG.

(Operation of SYNC field) The one-shot multivibrator 403 is triggered by the rising edge of the read data pulse train (Fig. 5 (a)) from the FDD, and outputs a pulse whose pulse width is 1/4 of the duration of 1-bit cell ( Fig. 5 (b)). This pulse train is always input to the phase comparison circuit 404, and is phase-compared with the window waveform (FIG. 5 (c)) in the SYNC field. The one-shot multivibrator 403 is a circuit inserted for time adjustment so that the read data pulse train from FDD is brought to the center of the window.

Since the trailing edge of the output waveform of the one-shot multivibrator in FIG. 5 (b) is delayed by 1/4 bit cell period from the rising edge of the read data pulse in FIG. 5 (a), SYNC
In order to bring the rising edge of the read data pulse in the center of the window waveform in the field, compare the phase of the rising or falling edge of the window waveform with the time 1/4 bit cell period behind the rising edge of the read data pulse, Lock the PLL. In the SYNC field,
Since the peak shift does not occur, the timing of the trailing edge of the output waveform of the one-shot multivibrator 403 (Fig. 5 (b)) and the rise or rise of the window waveform (Fig. 5 (c)) via the gate circuit 410. The downlink timing is compared in phase.

(Operation of data field) A peak shift occurs in the data field, and the pulse interval of the read waveform sometimes becomes half or twice the cycle of the window depending on the written data. It is not possible to directly compare the phase of the output of the multivibrator 403 and the window waveform. In the data field, the read data pulse shown in FIG. 5 (a) includes a peak shift, and its position is considerably different from the reference window waveform. FIG. 5 (d) output from the gate circuit 410 in order to surely bring the read data pulse to the center of the window.
The phase of the waveform of (1) and the output waveform of the one-shot multivibrator (FIG. 5B) are compared. The waveform of FIG. 5 (d) has a one-to-one correspondence between the read data pulse and the pulse number,
Moreover, since the trailing edge is a waveform that coincides with the rising or falling of the window waveform, by delaying the trailing edge with the waveform of FIG. 5 (d) as a pseudo data pulse (the waveform of FIG. 5 (e) is obtained. Correspondingly, the position of the pulse can be surely brought to the center of the window waveform.

This point will be described a little further with reference to FIG.
The waveform of FIG. 5D is output from the NAND gate ND1 of the gate circuit 410. Waveform shaping circuit 409 of FIGS. 4 and 6
FIG. 5 (e) shows a waveform obtained by inputting the waveform shown in FIG. 5 (d) from the gate ND1 as a pseudo data pulse and using a delay circuit configured by connecting a plurality of stages similar to the one-shot multivibrator 403. Form the waveform of. As will be described later, in the waveform of FIG. 5 (d), the rising edge is synchronized with the rising edge of the data pulse (FIG. 5 (a)), and the falling edge is the rising edge or rising edge of the window waveform (FIG. 5 (c)). It is in sync with the descent. Therefore, by delaying the trailing edge of the waveform of FIG. 5 (d) to generate the waveform of FIG. 5 (e), the read data pulse can be brought to the center of the window waveform.

(Operation of Gate Circuit 410) As shown in FIG. 6, the gate circuit 410 is a circuit for switching the signal output to the phase comparison circuit 404 according to the SYNC field / data field switching signal given to the terminal 402. Switching between flip-flops FF1 and FF2, which are set at the rising edge of the read data pulse train (Fig. 5 (a)) and are reset by the change in the window waveform (Fig. 5 (c)) (leading and trailing edges of the pulse). The switch is composed of FF3, AND gates AD1, AD2, and NOR gate NR1. The changeover switch has a role of selecting the window waveform of FIG. 5 (c) in the SYNC field, selecting the output signal of the gate ND1 in the data field and inputting it to the phase comparison circuit 404. The operation of the gate circuit 410 in the data field will be described with reference to the time chart of FIG. Flip flop FF
For 1, the level of the window waveform is set at the rising edge of the read data pulse and reset at the timing when the window waveform falls. If there is a read data pulse when the window waveform is low level, the negative output of Q is
The negative output of the Q becomes low level until the rising edge of the window waveform. The inversion level of the window waveform is set at the rising edge of the read data pulse, and the flip-flop FF2 is reset at the timing when the window waveform rises. If there is a read data pulse when the window waveform is high level, the negative output of Q becomes low level until the rising edge of the window waveform. The gate ND1 takes the logical product of the outputs of the flip-flops FF1 and FF2. Flip-flop FF3 is SYNC from terminal 402
Input the field / data field switching signal and output the selection signal to the gate AD1 or AD2. In the SYNC field, the window waveform is directly input to the phase comparison circuit 404 via the gates AD1 and NR1, and in the data field, the output of the gate ND1 is input to the phase comparison circuit 404 via the gates AD2 and NR1.

(Operation of Phase Comparison Circuit 404) The operation of the phase comparison circuit 404 will be described with reference to FIGS. FIG. 8 (a) shows the configuration of the phase comparison circuit, and FIG. 8 (b) shows the time chart of each signal. The output of the one-shot multivibrator 403 is input as the signal a, and the output of the gate circuit 410 is input as the signal b.
First, the flip-flop on the side where the pulse of the signal a and the signal b is input first is set at the trailing edge of the pulse. Next, the flip-flop on the delayed input side is set at the trailing edge of the pulse. The Q outputs c and d of the respectively set flip-flops are input to the NAND gate and generate the pulse e. The pulse e resets both flip-flops, and the signals c, d, and e immediately return to their original states. The output pulse e of the NAND gate and the Q output of the flip-flop set late are extremely thin pulses determined only by the delay of the circuit. In the phase comparison circuit, which pulse is input first is
The pulse width of the output signal is made different to obtain the detection result.
In FIGS. 4 and 8, the phases are compared at the falling edge of FIG. 5 (b) and (c) or (d), but in FIG. 6 the output of the gate circuit 410 is shown in FIG. ) And (d) waveforms are inverted and output, the falling edge of FIG. 5 (b) is compared with the rising edge of FIG. 5 (c) or (d), but what is essentially There is no change. That is, the phase comparison circuit 404 of FIGS. 4 and 6 outputs the output waveform of the one-shot multivibrator of FIG. 5 (a) and the window waveform of FIG. 5 (c) output by switching from the gate circuit 410 ( This means that the SYNC field) or the waveform (data field) of FIG. 5D is input as signals a and b, and the phases are compared.

(Operation of Switch Circuit 405) In the switch circuit 405, in the SYNC field, the gates G1 and G2 are selected by the SYNC field / data field switching signal, and the gates G1 and G2 receive the output of the flip-flop of the phase comparison circuit 404 and make an output. . In the data field, the gates G3 and G4 are selected by the SYNC field / data field switching signal, and the gate G3 or G4 receives the output of the flip-flop of the phase comparison circuit 404 and outputs it. S
In the YNC field, if the output phase of the one-shot multivibrator 403 is early, the output will be output from the gate G1 and operate to increase the oscillation frequency of the VCO 408. If the output phase is slow, the output will be output from the gate G2 and the VCO408 will be output. It operates to lower the oscillation frequency of. The response time at this time is
Determined by the time constant of the filter (high cutoff frequency) composed of R2 or R3 of LPF601 and R8 and C3. Similarly, for the data field, the output from the gate G3 or G4 is output, and the fast response (low cutoff frequency) filter selected by R4 or R5 and R6, C6, C2, R7, R8, C3 is selected. Raise or lower the oscillation frequency of.

Reference numeral 408 is a VCO, which varies the delay amount of the one-shot multivibrator of a plurality of stages by the output voltage of the LPF601 and feeds back the output of the second stage to oscillate.

After the data window is locked in the read data pulse train in the SYNC field, the waveforms of FIGS. 5B and 5D are phase-compared in the data field to obtain an output. The output waveform shaping circuit 409 moves the data pulse train to the center of the data window, removes the influence of peak shift, etc., and outputs a waveform as shown in FIG. 5 (e).

[Problems to be Solved by the Invention] Next, drawbacks of the conventional VFO circuit will be described.

As can be seen from FIG. 6, a drawback of the conventional VFO circuit is that it is difficult to integrate it into a semiconductor integrated circuit. In FIG. 6, 19 resistors and 6 capacitors are required as discrete components. It is also possible in the prior art to use these components as external components and the rest of the circuits as a semiconductor integrated circuit into one chip. However, this cannot fully utilize the features of the semiconductor integrated circuit. That is, the mounting space does not become small, the number of connecting points is large, the reliability is poor, and the number of mounting steps and the cost cannot be reduced. In addition, there are considerable restrictions when designing a chip for a semiconductor integrated circuit. First, when connecting from the inside of a semiconductor integrated circuit chip to an external component, the chip area becomes considerably larger than when connecting is not required. This is because the size of the pad for connection and the transistor size of the output buffer circuit are several tens of times larger than when the external connection is not required. Further, the cost of packaging the semiconductor integrated circuit increases.

A second drawback is that conventional circuits require adjustment after assembly. This is because the VCO does not have a stable and accurate circuit system.

It is an object of the present invention to provide a VFO circuit system that can be easily integrated into a semiconductor integrated circuit, reduce costs during implementation, and improve circuit reliability. Another object of the present invention is to reduce external parts of a semiconductor integrated circuit. Still another object of the present invention is to make the VFO circuit unregulated. Still another object is to provide a configuration in which the VCO sensitivity can be easily set.

[Means for Solving the Problem] The present invention has the same characteristics as the first and second control signal combining circuits, the first and second phase comparators, and the first and second LPFs. First and second phase-locked loops each having a first and second voltage-controlled oscillation circuit, reference signal generating means for outputting a reference signal, and phase-shifting the output signal of the first phase-locked loop In the VFO circuit including phase shift means, the second control signal synthesizing circuit synthesizes the output voltage of the second LPF and a reference voltage to control the oscillation frequency of the second voltage controlled oscillator circuit. A signal is output, the first control signal synthesis circuit converts the output voltage of the first LPF into a first current, converts the output voltage of the second LPF into a second current, and After adding the first current and the second current, the oscillation frequency of the first voltage controlled oscillator circuit is controlled. It is characterized by outputting a control signal.

[Embodiment] An embodiment of the present invention will be described with reference to FIGS. 1 and 2A and 2B. FIG. 2A shows the counter circuit 101 of FIG.
It is a figure which shows the specific example of. FIG. 2 (b) is 10 of FIG.
It is a figure which shows the concrete structure except 1,102,103,111,112. The operation of FIGS. 1 and 2 (b) will be described with reference to FIG. 5 as in the conventional example.

First, the configuration of the embodiment of the present invention will be described.

101 is a counter circuit, which is set at the leading edge of the read data pulse train from the FDD input to the terminal 119, starts counting the pulse train generated from the crystal oscillation circuit 102, and resets the pulse to be reset when a certain count is reached. Occur. Reference numeral 104 denotes a first phase comparison circuit having a configuration similar to that of the conventional example shown in FIG. 6 and the previously described FIG. 8, and since the same operation is shown, detailed description thereof will be omitted. 105 is a switch circuit and terminal 1
One of the low pass filters (LPF) 106, 107 is selected by the SYNC field / data field switching signal input to 20. The LPFs 106 and 107 have different pass bands, and SYN
In the C field, the first LPF 106 having a wide pass band is selected, and in the data field, the second LPF 107 having a relatively narrow pass band is selected. Reference numeral 108 denotes a first adder circuit that adds the output of the first LPF 106 or the second LPF 107 and the output of the third LPF 115 and inputs the result to the control terminal of the first voltage controlled oscillator circuit (VCO) 109. , And controls the oscillation frequency of the first VCO 109. 110 is a phase shift circuit. 111 is a differentiating circuit which emits a thin pulse at the trailing edge of the output signal from the gate circuit 103. 112 is a frequency divider circuit, 114 is a second phase comparison circuit, 11
Reference numeral 6 is a second adder circuit having the same characteristics as the first adder circuit 108, and the reference voltage Vr generated by the reference voltage source 117 and the third L
The output of PF115 is added to control the oscillation frequency of the second VCO 118. The characteristics of the second VCO 118 are designed to be the same as those of the first VCO 109. The present invention relates to a first PLL, that is, a first phase comparison circuit 104, a first or second LPF 106, 10.
7, a loop including the first VCO 109, and a loop including the second PLL, that is, the second phase comparison circuit 114, the third LPF 115, and the second VCO 118.

Next, the operation will be described.

First, the second PLL is locked to the frequency of the output signal of the frequency dividing circuit 112. The frequency divider circuit 112 divides the output signal of the crystal oscillator circuit 102 and outputs a signal of the free-run frequency required for the first VCO 109. Of course, when the second PLL is locked, the phase difference between the two signals input to the second phase comparison circuit 114 is fixed, and their frequencies are equal. That is, the second VCO also oscillates at the free-run frequency. Power-supply voltage,
Ambient temperature, change over time. Even if there are variations in the VCO constants due to factors such as the above, or variations in the VCO constants due to variations in the constants of the VCO components, the negative feedback loop causes the second
VCO118 of 3rd, so that it always oscillates at the free-run frequency,
LPF output is adjusted. Now, as shown in FIG. 1, the reference voltage Vr (for example, half of the power supply voltage) is applied to one input terminal of the second adder circuit 116, and the third LPF 115 is applied to one input terminal of the first adder circuit 108. When the output from the first VCO 109 is input, the first VCO 109 should oscillate at the free-run frequency when the output of the first LPF 106 or the second LPF 107 reaches the reference voltage Vr.

FIG. 2A is a diagram illustrating the counter circuit 101 in detail.
FIG. 9 shows an example of each output of the counter circuit 101 as a time chart. Upon receiving the read data pulse train (a) shown in FIG. 5, a pulse having a pulse width of 1/4 of the length of 1-bit cell (FIG. 5 (b)) is output. That is, the flip-flops 2020 and 2030 and the gate 2040 output a thin pulse at the leading edge of the read data pulse train input to the terminal 2060, reset the frequency dividing circuit 2010, and reset the flip-flop 2050. The output of the crystal oscillator circuit 102 is connected to the terminal 2080, and the frequency divider circuit 2010 divides the output signal of the crystal oscillator circuit. The flip-flop 2050 operates using the carry C output of the frequency divider circuit 2010 as a clock.

In the example of FIG. 9, the oscillation frequency of the crystal oscillation circuit 102 is 16 MHz, MF
The case of M (1 bit cell period 2 μs) was used. The count circuit 101 is a circuit for receiving the read data pulse shown in FIG. 5A and outputting a pulse having a width of 1/4 of the 1-bit cell period shown in FIG. 5B, that is, 500 ns.
In this embodiment, another configuration is adopted in place of the one-shot multivibrator shown in FIG. 6 of the conventional example. The flip-flop 2020 inputs the data of the read data pulse 2060 at the rising of the reference clock 2080 of the crystal oscillation circuit, and the flip-flop 2030 inputs the Q output of the flip-flop 2020 at the rising of the next clock 2080. As a result, NAND
The gate 2040 outputs a pulse, resets the divider circuit 2010 and the flip-flop 2050, and the divider circuit 2010 starts counting. A carry is output after the count is completed, and this carry changes the output 2070 of the flip-flop 2050.
That is, the output 2070 has a pulse (FIG. 5 (b)) from the rise of the read data pulse (FIG. 5 (a)) to the end of counting by the frequency divider circuit 1/4 bit cell period.
Is obtained. By adopting such a circuit system, a one-shot multivibrator circuit having a stable and accurate pulse width can be constructed. Also, as you can see from the comparison with the conventional example, the resistance
R1 and capacitor C1 are unnecessary.

The output of the counter circuit 101 is input to the phase comparison circuit 104,
Due to the function of the gate circuit 103, the first V in the SYNC field
The output waveform of CO109 (Fig. 5 (c)) and the waveform of Fig. 5 (d) in the data field are compared in phase. Gate circuit
Reference numeral 103 has the same configuration as that of the conventional example shown in FIG. The phase comparison result is connected to the first LPF 106 having a fast response in the SYNC field and the second LPF 107 having a slow response in the data field by the switch circuit 105 to filter the unnecessary high frequency component and
Is input to the first adder circuit 108 to control the oscillation frequency of the VCO 109.

The other input of the first adder circuit 108 receives the signal from the second PLL. As already mentioned, this signal is the first LP
When the output of F106 or the second LPF 107 is Vr, the VCO 109 oscillates at the free-run frequency. If the free-run frequency matches the window frequency, the first LPF1
The output voltage of 06 or the second LPF 107 becomes Vr.

The first phase comparison circuit 104 compares the phase of the read data pulse train with the phase of the window waveform, and if the former phase is early, it outputs an output from the gate G1 or G2 to produce a transistor T1.
Or make T2 conductive, charge the capacitor C202 of LFP209, raise the gate voltage of transistor T16, and increase the first VCO10.
Increase the oscillation frequency of 9. On the other hand, if the window waveform is earlier, the output is output from the gate G3 or G4 to make the transistor T3 or T4 conductive, and the capacitor of the LFP109
The electric charge is discharged from C202, the gate voltage of the transistor T16 is lowered, and the oscillation frequency of the first VCO 109 is lowered. Now
If the source potential of the transistor T1 or T2, T3 or T4 VDD respectively, and V SS, a current value to be charged by the T1 or T2 is proportional to VDD-Vr, and the current value to be discharged by T3 or T4 is Vr -Proportional to Vss. If Vr is set to the average value of VDD and Vss, it will flow into the LPF in the steady state.
The flowing currents can always have the same absolute value. Moreover, LPF
Since the output can be very close to Vr in the steady state, if the charge pump circuit system in which the capacitor is charged and discharged by the transistor as shown in FIG. It becomes unnecessary to use an active filter as LPF. This greatly facilitates integration into an integrated circuit.

The output of the first VCO 109 is fed back to the first phase comparison circuit 104 via the gate circuit 103 to form a loop. Thus, a stable and accurate window can be formed.

In the conventional example, the one-shot multivibrator is used as the output waveform shaping circuit 409 to delay the waveform of FIG. 5 (d) to form the waveform of FIG. It is moved to the center of the window in (c). In the embodiment of the present invention, waveform shaping is performed by a different method. That is, the differentiating circuit 111 produces a thin pulse shown in FIG. 5 (g) from the trailing edge of the waveform shown in FIG. 5 (d). This differentiating circuit is a flip-flop shown in FIG.
It can be easily realized by adopting the same circuit configuration as that of the 2020, 2030 and the gate 2040. The read data pulse train has the waveform shown in Fig. 5 (g), and since it did not pass through the delay circuit, the resistors R16, R17 and capacitor C as shown by 409 in Fig. 6 were used.
No need for 5, C6. On the other hand, in order to place the read data pulse train (FIG. 5 (g)) at the center of the window, in the embodiment of the present invention, the window waveform is phase shifted by 90 degrees (270 degrees) by the phase shift circuit 110 (fifth phase). See FIG. (F)). This phase shift circuit can be easily constructed if the 1/2 frequency divider circuit is composed of a master-slave flip-flop, because the phases of the output waveforms of the master and slave are different by 90 degrees. The gate side 103 outputs the M output of the master side of this flip-flop.
By feeding back to and outputting the slave side Q output to the terminal 121, the waveforms of FIGS. 5 (c) and 5 (f) can be easily obtained.

Above, LPF106,107,115, adder circuit 108,116, reference voltage source 1
17, all circuits except VCO109,118 and crystal oscillator circuit 102 can be configured by digital circuits, and no external parts are required for the semiconductor integrated circuit, and VCO does not require high accuracy and stability. Explained.

Next, according to FIG. 2 (b), the phase comparison circuits 104 and 114
It will be described that the VCOs 109 and 118 can be simplified according to the present invention and can be easily integrated into an integrated circuit.

The figure shows the phase comparison circuits 104 and 114, the switch circuit 105, and the LPF10.
6,107,115, adder circuits 108,116, VCOs 109,118, phase shift circuit 11
FIG. 2 is a diagram detailing 0, and in order to correspond to FIG. 1 as much as possible, each block surrounded by an alternate long and short dash line has the same number. However, since LPFs 106 and 107 share a part, both are designated as 209.

Further, as described above, since the phase shift circuit 110 can be realized only on the slave side of the master-slave flip-flop 205 in the VFO 109, the alternate long and short dash line is drawn to divide the flip-flop 205. A master-slave flip-flop is used to divide by 1/2. In FIG. 2B, one flip-flop is shown, but the inside is composed of two flip-flops, a master and a slave. The output signals of the master and slave flip-flops are 90 degrees out of phase with each other. Therefore, the M output of the master flip-flop is pulled out for the phase shift of 90 degrees.

The insides of the phase comparison circuit 114 and the addition circuit 116 are the same as those of the phase comparison circuit 104 and the addition circuit 108, respectively, so that the insides are omitted. Since the VCO 118 is the same as the VCO 109 and the master flip-flop of the phase shift circuit 110, the inside is omitted.

The terminal 201 is connected to the counting circuit 101. Also terminal 202
Is connected to the gate circuit 103. Further, the terminal 203 is connected to the frequency dividing circuit 112, and the terminal 204 is connected to the gate circuit 103 as an input signal.

The switch circuit 105 receives the SYNC field / data field switching signal input to the terminal 120 from the NAND gates G1, G2,
Switch between G3 and G4. Gate G2 in SYNC field,
G3 is selected and transistors T1 and T3 make resistors 201, R
The LPF composed of 204 and the capacitor C202 is charged and discharged. In the data field, the gates G1 and G4 are selected, and the transistors T2 and T4 enable resistors R202, R203, R204 and capacitors.
Charge and discharge the LPF consisting of C201 and C202. That is, the switch circuit 105 is an LPF having a fast response configured by the resistors R201, R204 and the capacitor C202, or the resistors R202, R203, R202.
The phase comparison result is transmitted to either one of the LPF having a slow response, which is constituted by 204 and capacitors C201 and C202.

108 and 116 are adder circuits that add the drain currents of the transistors T16 and T17 that input the control signal output from the LPF to their gates, and convert them into a voltage by the transistor T5.
Control VCO109. Transistors T5, T6, T7, T8, ... T
If T9, T18, T19, T20, ... T21 are the same constant, the drain current becomes the same as that of the transistor T5 in the saturation region.

In the present embodiment, by using the first adder circuit 108 shown in FIG. 2B, the voltages of the respective control signals input to the gates of the transistors T16 and T17 are set to V1 and V1.
2, the voltage-current conversion coefficient in the adder circuit is a, b, and the adder circuit and VC
The oscillation frequency fVC
O is fVCO = Kv (aV1 + bV2) Kv, a, b is expressed as a constant.

As understood from this equation, it is understood that the sensitivity of the control signal can be set independently of the oscillation frequency of the VCO. Two
If the adder circuit and the VCO have good symmetry, the pair of PLLs has no drift or initial variation even if a VCO with poor characteristics that could not be used in the conventional PLL is used. In this case, a VCO that oscillates at a free-run frequency can be realized. With this configuration, the first PLL
VCO109 can be stabilized. Two sets of VCO and adder circuit or PLL
If they are formed adjacent to each other on one semiconductor substrate, similar characteristics can be obtained, and the above condition that the symmetry is good can be easily achieved.

That is, the drain current of the transistor can be controlled by the gate voltage of the transistors T16 and T17. The transistors T10, T13, T11, T14 ... T12, T15 form an inverter, and odd-numbered stages are connected in a ring shape to form a ring oscillator. Since the source of the transistor of each inverter of the ring oscillator has a current limiting transistor, the gate voltages of the transistors T16 and T17 are converted into drain currents and added, and the added current is converted into a voltage by the transistor T5. The drain current of the current limiting transistor is controlled by this voltage, the response speed (signal delay amount) in each stage inverter of the ring oscillator is controlled, and as a result, the oscillation frequency of the ring oscillator is controlled. The output of the ring oscillator is a buffer
The duty ratio is adjusted by dividing by 1/2 by the flip-flop 205 via 206. By using the output 204 on the master side of the flip-flop 205, a new phase shift circuit is not required.

Since the VCO 109 is stabilized by the method described above, the ring oscillator, which normally has a problem of stability, can be adopted without any problem. The link oscillator can be constructed by connecting an odd number of stages of inverters, and since there is no external component such as a capacitor in the semiconductor integrated circuit, it is very easy to form an integrated circuit.

A reference voltage source 117 generates a reference voltage by dividing the power supply voltage with resistors R206 and R207. If the resistors R206 and R207 have good relative accuracy, the generated voltage accurately divides the power supply voltage, so that it is easy to make them in the semiconductor integrated circuit. It goes without saying that a voltage generated by a Zener diode or the like may be used. 115 is the third LPF. When the current of the current source 207 is Io, the power voltage of Io is converted by the transistor T22 to control the gate voltage of the transistors T26 and T28 and limit the channel current of the transistors T26 and T28.
If the constants of the transistors T22, T26, T28 are the same, the current limit value is Io. Transistor T23 converts Io into a voltage and limits the channel current of transistor T24. If the transistors T26, T23 and T24 have the same constant, the current limit value is Io. The transistors T25 and T27 are called a charge pump circuit, and the transistors T1 and T3 in the switch circuit 105 are
Alternatively, it is a switch having the same function as T2 and T4, and the capacitor C203 is charged and discharged by the transistors T25 and T27 so as to delay or advance the output phase of the VCO 118 according to the phase comparison result of the phase comparison circuit 114, and the second addition The potential input to the circuit 116 is controlled. That is, the LPF 115 is composed of the current limiting transistor T24 or T28, the resistor R205, and the capacitor C203. Since the currents of the transistors T24 and T28 are limited to Io, the terminal potential of C203, that is, the addition circuit 116.
Even if the input voltage of R2 changes, the amount of charge transferred from the transistor T25 or T27 to R205 and R203 does not change. That is, the terminal potential of C203 can change significantly due to the fluctuation of the constant of the VCO 118, but the constant fluctuation such as the response of the second PLL system due to it can be suppressed to the minimum.

Incidentally, comparing FIG. 1 and FIG. 2 (b), the third LPF115
In, the output port of the signal input to the first addition circuit 108 and the output port of the signal input to the second addition circuit 116 are different. Since the resistor R205 is inserted so that the second PLL operates stably, it can be considered that R205 is removed from the same place in principle as shown in FIG.

It can be seen from FIG. 2 (b) that this can be realized by almost complementary MOS integrated circuits. Of course, the same is true when bipolar or other semiconductor processes are used. But it still seems to require 7 resistors and 3 capacitors. However, as described above, the resistors R206 and R207 need only be able to secure the relative accuracy, and thus can be built in the semiconductor integrated circuit. Also, the required accuracy of C203 and R205 is fairly rough, and this can also be built in. Similarly, the resistors and capacitors in the LPF209 do not require much precision and can be built in the semiconductor, but it is necessary to change the filter constant depending on the type (size, etc.) of the FDD connected to the semiconductor integrated circuit. It would be better to attach it externally.

In addition, all or part of the frequency dividing circuit 112 is inserted in series at the position of the terminal 113 in FIG. 1 and the output of the crystal oscillation circuit 102 is directly input to the input side of the second phase comparison circuit 114, or If the remaining part of the frequency divider circuit 112 pushed into 113 is inserted and input through this, the oscillation frequencies of the VCOs 109 and 118 can be made higher by the frequency division number of the frequency divider circuit moved to the terminal 113. The time constant in the third LPF 115 can be reduced. By doing so, the capacitor C203, the resistor R205, etc. can be made smaller, and the semiconductor integrated circuit can be further facilitated.

The present invention requires an expensive and stable oscillation circuit like the crystal oscillation circuit 102 as compared with the conventional example. FDD in the conventional example
Such an oscillating circuit is not required when reading data from, but is required when writing. When the present invention is carried out, the crystal oscillation circuit used at the time of writing can be used also at the time of reading, so that it does not become a factor of complication or cost increase, and there is no obstacle in carrying out the present invention. Further, in the present invention, it may be possible that some people think that the addition of the second PLL makes it complicated and increases the cost of the semiconductor integrated circuit.

However, the opposite is true, and since the number of externally attached parts is greatly reduced, the area of the bond pad for input / output to the semiconductor integrated circuit and the area of the transistor for the input / output buffer can be greatly saved. These are large-sized portions in the semiconductor integrated circuit, and their occupied area is usually considerably larger than the entire area of the second PLL circuit. Therefore, the cost of the semiconductor integrated circuit can be reduced by implementing the present invention.

Furthermore, since the number of external parts is greatly reduced, the cost of parts, the cost for assembling, the reduction of mounting space, and the enhancement of reliability can be achieved. Also, since the VCO automatically adjusts the free-run frequency, no adjustment man-hours are required during assembly. In addition, by positively using the signal of the crystal oscillation circuit that emits the signal of the reference frequency, for example, by replacing the one-shot multivibrator of the conventional circuit with the counter circuit, the circuit can be made into a digital circuit, and the precision and the number of parts can be improved. Can be reduced.

[Effects of the Invention] As described above, according to the present invention, the second PLL is added, the signal from the second PLL and the LPF output of the first PLL are converted into a current, and the addition processing is performed. The circuit can be stabilized by the VCO circuit, the VCO sensitivity can be set for each control signal, and a PLL with good characteristics, and thus a VFO circuit, can be obtained. It becomes extremely easy to make.

If the present invention is implemented, the VFO circuit can be largely integrated into a semiconductor integrated circuit, simplification of device design, high reliability of the device, reduction of assembly man-hours, downsizing of the device, and cost reduction can be realized. unfathomable.

The present invention can also be applied to VFO circuits for hard disks and semiconductor integrated circuits for other PLL circuits.

[Brief description of drawings]

1 and 2 (a) and (b) are diagrams showing a VFO circuit according to the present invention. 3 (a) and 3 (b) are time charts for explaining the recording format of the floppy disk. 4 and 6 are diagrams illustrating a conventional VFO circuit. FIG. 5 is a time chart for comparing and explaining the operation of the conventional VFO circuit according to the present invention. FIG. 7 is a time chart for explaining the operation of the gate circuit. FIGS. 8A and 8B are views for explaining the configuration and operation of the phase comparison circuit. FIG. 9 is a time chart for explaining the operation of the counting circuit. 101 …… Count circuit 102 …… Crystal oscillator circuit 103 …… Gate circuit 104,116 …… Phase comparison circuit 106,107,115,209 …… LPF 108,116 …… Adding circuit 109,118 …… VCO 110 …… Phase shift circuit 111 …… differential circuit

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https://patents.google.com/patent/JPH0712146B2/en

크게 종요한 포인트는 아니지만.. 일단 특허는 만료된듯 합니다. 어떻게 보면 플로피 디스크 드라이브 관련된 내용이니 굳이 유지할 필요는 없다고 생각도 되지만요. :D